SRAM Renesas RMLV0816B

SRAM Renesas RMLV0816B

Company Renesas Electronics has announced the release of five new models chips static random access memory with low power consumption (Advanced LP SRAM), belonging to the series and RMLV0816B RMLV0808B. They have a density of 8 Mbps and manufactured according to the norms of 110 nm.
Chip SRAM Renesas RMLV0816B and RMLV0808B produced at rates of 110 nm

Why should use a “rough” manufacturing process when the chips for consumer mobile electronics has long been available on the more subtle rules?

The thing is that by increasing the elements is possible to increase radiation resistance. According to the manufacturer, the new memory excluded one-time failures (Soft Error or Single-Event Upset, SEU) and latching transistors (Latch-up).

The reason for failure is a single current pulse that occurs when it enters the cell ion. He takes the cell to the opposite state, but the scheme is still in working condition. As transistor sizes in the new chips are relatively large, to switch requires a large charge that the likelihood of failure tends to zero. Furthermore, in the scheme introduced special cell capacitor. In contrast to error correction using the ECC, this approach allows to prevent the simultaneous occurrence of multiple errors. Using this and other techniques for assessing Renesas, possible to obtain the same degree of radiation hardness, as in the case of chips produced at rates of 150 nm.

With regard to latching transistors, its cause is called the ion current pulse, which leads to opening thyristor-like circuit formed by parasitic structures of the pairs of transistors of various types. As a result, it clicks current through the transistors is increasing even after cessation of exposure of the ion, which can lead to overheating and damage the chip failure. The new memory on a monocrystalline substrate formed only transistors of n-channel type transistors and p-channel type TFTs is formed as using polycrystalline silicon, which excludes the formation of the parasitic thyristor structures and essentially eliminates the risk of latching transistors. Along the way, it is possible to reduce the cell area and the size of the chip, bringing these figures to those of memory manufactured on 65nm.

Current consumption in the standby mode is less than 2 mA at a temperature of 25 ° C, making the chip suitable for storing data in devices with battery backup.

The plans Renesas – release this memory density of 16 Mbps.

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